FPGA Implementation of Residue Number System Structures
نویسندگان
چکیده
In this paper we explore the feasibility of implementing Residue Number System (RNS) based DSP algorithms on Lookup table based Field Programmable Gate Arrays (FPGAs). In this process, Binary Decision Diagrams are used for logic representation, and a new minimizing algorithm for incompletely specified functions is introduced. A sample residue arithmetic based design is presented along with promising simulation results. The architectural model is based on a previously reported bit-level systolic array cell.
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